Integrated Circuit Layout Designer Salary in Arizona - State Average

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Average Salary for Integrated Circuit Layout Designer in Arizona - State Average

The average salary of a(n) Integrated Circuit Layout Designer in Arizona - State Average is $61,454.

The average hourly rate of a(n) Integrated Circuit Layout Designer in Arizona - State Average is $29.55.

The average bonus of a(n) Integrated Circuit Layout Designer in Arizona - State Average is $1,499.00.

Job Description:

Designs layout for integrated circuits (IC), according to engineering specifications, using computer-assisted design (CAD) equipment and software, and utilizing knowledge of electronics, drafting, and IC design rules (standard IC manufacturing process requirements). Reviews and analyzes engineering design schematics and supporting documents, such as logic diagrams and design rules, to plan layout of IC. Confers with engineering staff to resolve design details or problems. Excludes supervisory positions. Documents engineering specifications and enters into computer memory of CAD equipment and develops configurations on equipment display screen of IC logic elements (basic components of integrated circuit, such as resistors and transistors) for all IC layers, using keyboard, digitizing work aids (light pen or digitizing tablet), and engineering design schematics, and applying knowledge of design rules, programmed CAD functions, and electronics. Compares logic element configuration on equipment display screen with engineering schematics and redesigns or modifies logic elements, as needed, using digitizing work aids, keyboard, and programmed CAD functions. Lays out, redesigns, and modifies arrangement and interconnections of logic elements for each layer of integrated circuit, using digitizing work aids, keyboard and programmed CAD functions listed on display screen. Keys in specified commands, using CAD equipment keyboard, to test final IC layout for errors in design rules, using design rule software package. May generate copy of logic element design, using plotter to verify that logic element design copy meets design requirements and for use in laying out IC layer design for Very Large Scale (VLS) integrated circuits. May generate tape of final layout design for use in producing photo masks for each layer of IC, using CAD equipment. May program CAD equipment to change CAD functions listed on display screen, using keyboard. Less

Designs layout for integrated circuits (IC), according to engineering specifications, using computer-assisted design (CAD) equipment and software, and utilizing knowledge of electronics, drafting, and IC design rules (standard IC manufacturing process requirements). Reviews and analyzes engineering design schematics and supporting... More

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